1. Field of the Invention
The present invention relates to the field of semiconductor memory devices, and more particularly to memory decoder circuits.
2. Prior Art
In a typical semiconductor memory, contents of the memory are couple to other devices through various interfacing means. Well-known architecture developed for semiconductor memories incorporate the use of sensing amplifiers to read the information stored in various memory cells. Data is written into and stored in a memory cell, and when this data is to be read from each of these memory cells, a pair of bit lines couple the memory cell to its appropriate sensing amplifier. The sensing amplifier reads the state of the bit lines and provides the results as an amplified signal on a distribution bus. In a typical memory array architecture, a plurality of memory cells are arranged in an array and a column of memory cells are coupled to a sense amplifier through a decoder circuit. A word line selects memory cells of a given row of an array and one of the decoder circuits is selected to couple a desired column to the sense amplifier.
One such prior art architecture uses static random access memory (SRAM) cell. One such SRAM architecture is described in U.S. Pat. No. 4,096,584, entitled LOW POWER/HIGH SPEED STATIC RAM, which is as igned to the assignee of the present application. Generally, the column decoder circuit switches the memory cell bit line pairs onto a pair of output lines for transferring data on the bit lines to the sense amplifier. Further, the pair of bit lines and output lines are comprised of a data line and its compliment line.
In the prior art when bit lines are coupled to the output lines, bit line and output line capacitances are shorted together when its respective column decode circuit is selected. Current coupling the data from the SRAM cell will need to move the total capacitance of the bit line and the output line in order to develop a signal for sensing by the sense amplifier. If the bit line capacitance and the output line capacitance are isolated from each oteer, then a signal current of the memory cell would need to drive less capacitance to develop a signal on the output lines for the sense amplifier and decrease the time required to transfer the data from the memory cell to the sense amplifier.
Further, in some prior art decoding circuits using metal-oxide semiconductor field-effect transistor (MOSFET) switches, a resistance is introduced by the presense of these MOSFETs. The MOSFET resistance combines serially with the output line capacitance, therein causing an introduction of a RC time constant which further delays the transfer of the signal from the bit line pair to the output line pair. The delay caused by the RC time constant occurs, because in the prior art SRAM decoder circuits the bit lines are typically driven by a voltage source and the output lines are coupled to a high input impedence sense amplifier.
In addition, prior art SRAM cells utilizing no capacitative isolation between the bit line and the output line pairs are sensitive to power supply variations. For example, when the power supply voltage ramps quickly from its operating value, the bit lines are left at their original voltage level because of a lack of a discharge path for the bit lines. Therefore, prior art SRAM cells are more sensitive to supply voltage variations and can provide erroneous readings if operating in an unstable environment.
Finally, older techniques have used high input impedance differential sense amplifier with level shifting that does not provide as fast a response as a low input impedance sensing amplifier, because the high input impedence devices are typically voltage driven and the overall amplifier requires mor stages of amplification.
It is appreciated then that what is required is a SRAM decoding circuit which is capable of isolating the bit line capacitance from the output line capacitance; and is further capable of driving a low input impedance sensing amplifier, as well as providing a circuit which is generally immune from sudden power supply voltage variations.